1. Field of the Invention
The present invention relates to a semiconductor package and method for fabricating the same.
2. Discussion of Related Art
Semiconductor packages such as ball grid array (BGA) package, chip scale package and micro ball grid array package reflect the trend towards of miniaturization and thinness in packaging. Furthermore, today""s semiconductor chips are generating increasing amounts of heat during the operation of the semiconductor chip.
FIG. 16 illustrates a conventional BGA semiconductor package. A semiconductor chip 2xe2x80x2 having a plurality of electronic circuits integrated therein and input/output pads 4xe2x80x2 thereon is mounted at the center of the top face of a relatively thick printed circuit board 10xe2x80x2. An adhesive layer 91xe2x80x2 attaches chip 2xe2x80x2 to circuit board 10xe2x80x2. Printed circuit board 10xe2x80x2 is composed of a resin film 11xe2x80x2 as a base layer. Resin film 11xe2x80x2 has a circuit pattern layer including bond fingers 12xe2x80x2, connector parts 13xe2x80x2 (e.g., conductive traces) formed on the top side thereof, and ball lands 15xe2x80x2 in grid shape formed on the bottom side thereof. The circuit pattern layer is formed around semiconductor chip 2xe2x80x2 in radial form. Bond fingers 12xe2x80x2, connection parts 13xe2x80x2 and ball lands 15xe2x80x2 constituting the circuit pattern layer are formed from a conductive metal material such as copper or the like. Connection parts 13xe2x80x2 located on the top of resin film 11xe2x80x2 and ball lands 15xe2x80x2 disposed on the bottom thereof are electrically connected to each other through a conductive via hole 14xe2x80x2. A portion of the top and bottom sides of resin film 11xe2x80x2, other than the region on which bond fingers 12xe2x80x2, ball lands 15xe2x80x2 and semiconductor chip 2xe2x80x2 are disposed, is coated with a cover coat 16xe2x80x2 to protect the circuit pattern layer from external environment and prevent short-circuiting.
Moreover, input/output pads 4xe2x80x2 of semiconductor chip 2xe2x80x2 are connected to bond fingers 12xe2x80x2 formed on printed circuit board 10xe2x80x2 through conductive wires 6xe2x80x2. The upper side of printed circuit board 10xe2x80x2, including semiconductor chip 2xe2x80x2, is encapsulated with an encapsulant 20xe2x80x2 so as to protect semiconductor chip 2xe2x80x2, conductive wires 6xe2x80x2 and their bonded portions from harmful external environments. Conductive balls 30xe2x80x2 are fused to ball lands 15xe2x80x2 formed on the bottom face of printed circuit board 10xe2x80x2 so as to be able to transmit electric signals between semiconductor chip 2xe2x80x2 and a mother board (not shown) when semiconductor chip 2xe2x80x2 is mounted on the mother board.
In such a conventional BGA semiconductor package, electric signals from semiconductor chip 2xe2x80x2 are delivered to the mother board through input/output pads 4xe2x80x2, conductive wires 6xe2x80x2, bond fingers 12xe2x80x2, connection parts 13xe2x80x2, via hole 14xe2x80x2, ball lands 15xe2x80x2 and conductive balls 30xe2x80x2 sequentially, or they are transmitted reversely. However, in the conventional BGA package, semiconductor chip 2xe2x80x2 is mounted on the top of relatively thick printed circuit board 10xe2x80x2, which increases the thickness of the semiconductor package and makes it unsatisfactory in applications requiring a small and thin semiconductor package. Consequently, the conventional BGA package is not suitable for small electronic devices such as cellular phone and pager.
Further, as described above, the amount of heat generated per unit volume during the operation of the semiconductor chip is relatively high, but the heat spreading efficiency is low, which deteriorates the electrical performance of the semiconductor chip and, according to circumstances, may lead to failure. There has been proposed a semiconductor package having a heat spreading plate for easily emitting heat generated during the operation of the semiconductor chip. In this case, however, mounting of the heat spreading plate increases the thickness of the semiconductor package and manufacturing cost.
Meanwhile, the currently manufactured semiconductor package is generally 5xc3x975 mm in area and 1 mm in thickness. Accordingly, a circuit board strip capable of simultaneously fabricating tens to hundreds of semiconductor packages has not been realized so far, even though it is ideal for as many semiconductor packages as possible to be made from a single circuit board strip with a conventional size. This is because of poor wire bonding due to warpage caused by a difference in the thermal expansion coefficients between different materials constituting the circuit board strip, inferior molding, and/or damage to the semiconductor chip due to momentary discharging of static electricity accumulated during the molding process.
FIG. 17 is a bottom view illustrating a conventional semiconductor package using a circuit board unit 10xe2x80x2 having a runner gate. With reference to FIG. 17, runner gate RG is formed at a corner of circuit board unit 10xe2x80x2. Runner gate RG functions as a passage through which a melted molding resin at a high temperature and pressure is poured into the package for forming a resin encapsulant 20xe2x80x2 that protects semiconductor 2xe2x80x2 from the external environment. Conductive balls 30 are formed as external input/output terminals after the molding step.
FIG. 18 is a cross-sectional view illustrating a molding step in the fabrication of the conventional semiconductor package. Referring to FIG. 18, semiconductor chip 2xe2x80x2 is mounted on printed circuit board unit 10xe2x80x2. Wire bonds 6xe2x80x2 are attached between a circuit pattern formed on unit 10xe2x80x2 and semiconductor chip 2. The assembly is located between a top die TD and bottom die BD, which is filled with melted resin encapsulant 20. Specifically, top die TD has a cavity CV with a predetermined-size space so that encapsulant 20xe2x80x2 can encapsulate semiconductor chip 2xe2x80x2 therein. Cavity CV is connected to a gate G and runner R (corresponding to runner gate RG of FIG. 17) to allow melted encapsulant 20xe2x80x2 to flow from a resin port (not shown) through runner R and gate G to cavity CV. Runner gate RG is conventionally composed of a plated region using gold.
The conventional method of fabricating a semiconductor package, as mentioned above, has a shortcoming in that the runner gate should be formed on one side of the circuit board in the step of molding. This runner gate raises the manufacturing cost of the package because it is formed by plating a metal such as gold whose strength of adhesion to the encapsulant is smaller than that of the circuit board. Further, any increase in the number of or change in the location of the conductive balls 30xe2x80x2 is limited since the ball lands cannot be formed at the runner gate region.
Moreover, providing a mold having the runner and gate with a shape corresponding to the runner gate of the circuit board, i.e., top die, can be complicated and costly. In addition, if the runner gate of the circuit board during molding, it is possible that the melted encapsulant will bleed out toward the ball lands. This obstructs the fusing of conductive balls 30xe2x80x2 to the ball lands.
U.S. Pat. No. 5,620,928 provides another example of a conventional package.
Accordingly, the present invention is directed to a semiconductor package and method for fabricating the same that substantially obviates limitations and disadvantages of the related art.
A first objective of the present invention is to provide a very thin semiconductor package.
A second objective of the present invention is to provide a semiconductor package having excellent heat spreading performance.
A third objective of the present invention is to provide a semiconductor package having excellent heat spreading performance, wherein the backside of the chip may be grounded and marked.
A fourth objective of the present invention is to provide a method for fabricating the semiconductor package according to the first, second and third objectives.
Additional objectives, features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
In one embodiment, a semiconductor package within the present invention includes: a semiconductor chip having a first face and a second face, the first face having a plurality of input/output pads formed thereon; a circuit board composed of a resin film having a first face and a second face, a circuit pattern layer including a plurality of bond fingers and ball lands, and a cover coat covering the circuit pattern layer with the plurality of bond fingers and ball lands selectively exposed, the circuit pattern layer being formed on the first face of the resin film, the circuit board having a through hole at the center thereof, the semiconductor chip being placed in the through hole; an electrical conductor such as bondwires that electrically connects the input/output pads of the semiconductor chip to the bond fingers of the circuit board; an encapsulant for encapsulating the semiconductor chip, connection means and a part of the circuit board; and a plurality of conductive balls fused to the circuit board. Such a package may be very thin.
In the various embodiments of packages within the present invention, the second face of the semiconductor chip in the semiconductor package may be externally exposed, or a metal thin film may be formed on the second face of the semiconductor chip and/or the second face of the resin film, or a heat spreading plate is formed on the second face of the resin film. Such packages provide excellent heat spreading performance.
In other package embodiments within the present invention, the second face of the semiconductor chip and the second face of the resin film of the semiconductor packages are covered by a metal thin film or conductive ink marking, which allows an electrical connection thereof to a ground voltage supply or some other voltage supply.
The present invention also provides a method for fabricating a semiconductor package. One embodiment within the present invention includes the steps of: providing a circuit board having a plurality of bond fingers and ball lands, the circuit board having a through hole formed at the center thereof; locating a semiconductor chip having a plurality of input/output pads at one face thereof in the through hole of the circuit board; electrically connecting the input/output pads of the semiconductor chip to the bond fingers of the circuit board through an electrical conductor such as bond wires; encapsulating the semiconductor chip, conductors, and a predetermined region of the circuit board with an encapsulant; and fusing conductive balls to the ball lands of the circuit board, to form input/output terminals.
Another embodiment of a method within the present invention for fabricating a plurality of semiconductor packages includes steps of: providing a resin film and a matrix type circuit board strip for the semiconductor packages, the resin film forming a main strip, the main strip being composed of a plurality of substrips connected in one body, each substrip having a plurality through holes, equally spaced apart, each through hole being a region where a semiconductor chip will be placed, the circuit board strip having a conductive circuit pattern formed on the resin film; attaching a closing means to one face of the circuit board strip so as to close all the through holes formed in each substrip thereof; locating the semiconductor chip in each through hole, to attach it onto the closing means; connecting the semiconductor chip and the circuit pattern to each other through an electrical conductor; charging the through holes with an encapsulant for protection of the semiconductor chip and connection means from external environment; removing the closing means from the circuit board strip; fusing conductive balls as external input/output terminals; and cutting the portion of the resin film around each through hole, to separate the semiconductor packages.
In one embodiment of the above method, the closing means has an opening as a mold gate. In another alternative embodiment, a mold gate G is formed above a cavity CV of a top die TD so as to minimize wire sweeping phenomenon during molding process.
The circuit board may have a metal thin film on the second face of the resin film. The circuit pattern layer formed on the first face of the resin film may be connected to the metal thin film formed on its second face through a conductive via hole. Further, a cover coat may be formed on the metal thin film formed on the second face of the resin film. Alternatively, a heat spreading plate may be formed on the second face of the resin film.
The circuit board may have the circuit pattern layer having the plurality of ball lands formed on the second face of the resin film. In such an embodiment, the circuit pattern layer formed on the first face of the resin film is connected to the circuit pattern layer having the plurality of ball lands formed on its second face through a conductive via hole. Further, a cover coat may be formed on the circuit pattern layer formed on the second face of the resin film exposing the lands. A heat spreading plate may be placed on the second face of the circuit board.
The semiconductor packages described above can be constructed in such a manner that the first face of the semiconductor chip and the face of the circuit board on which the bond fingers are formed face the same direction, and the second face of the semiconductor chip, the face of the circuit board on which the bond fingers are not formed and one face of the encapsulant are in the same plane.
An insulating film may be attached to the second face of the semiconductor chip, the face of the circuit board on which the bond fingers are formed and one face of the encapsulant. The insulating film may be an ultraviolet tape whose adhesion characteristic is weakened or lost when ultraviolet rays are irradiated thereto.
A conductive metal thin film may be attached to the second face of the semiconductor chip, the face of the circuit board on which the bond fingers are not formed and one face of the encapsulant. The conductive metal thin film may be formed from copper.
The first face of the semiconductor chip and the face of the circuit board on which the bond fingers are formed may face the same direction, and the second face of the semiconductor chip, one face of the heat spreading plate formed one side of the circuit board and one face of the encapsulant may be in the same plane.
An insulating film may be attached to the second face of the semiconductor chip, one face of the heat spreading plate formed one side of the circuit board and one face of the encapsulant, which are located in the same plane. The insulating film may be an ultraviolet tape.
A conductive metal thin film may be attached to the second face of the semiconductor chip, one face of the heat spreading plate formed on one side of the circuit board and one face of the encapsulant which are located in the same plane. The conductive metal thin film may be formed from copper.
A conductive ink film with a design may be formed on the second face of the semiconductor chip, one face of the encapsulant and a part of the face of the circuit board on which the bond fingers are not formed which form the same plane.
The conductive ink film having a design can be formed on the second face of the semiconductor chip, one face of the heat spreading plate formed on one side of the circuit board and one face of the encapsulant which are located in the same plane.
The conductive ink film having a design can be formed only on the second face of the semiconductor chip, a part of one face of the heat spreading plate formed on one side of the circuit board and one face of the encapsulant which are located in the same plane.
The conductive balls may be fused to the ball lands formed on the second face of the resin film of the circuit board.
There is explained below a circuit board strip used for the method of fabricating a semiconductor package of the present invention. A ground ring may be electrically connected to at least one circuit line constituting the circuit pattern. The ground plane is exposed out of the cover coat and electrically connected to the ground ring.
The closing means, such as cover lay tape, can be attached to one face of the circuit board strip constituting the main strip. Separate closing means may be attached to the substrips in one-to-one relation with them. One side of each of the separate closing means covers a slot formed between neighboring substrips. Alternatively, a single one-body closing means having a similar size to the circuit board strip, the one-body closing means having a cutting pin hole line located between neighboring substrips corresponding to the slot. The above designs minimize the warpage cause by a difference in coefficient of the thermal expansion which increases with the length, previously preventing detects generated during the fabrication of the semiconductor package.
The closing means has an opening as a mold gate for each package, the opening being formed at a part of the region disposed between the edge of the area where the semiconductor chip is mounted and the edge of each of the through holes within each substrip. The opening has a shape selected from circular, square and bent rectangular forms, but the present invention is not restricted to these shapes.
In the method for fabricating a semiconductor package to achieve the fourth objective of the present invention, a through hole closing means may be attached to the face of the circuit board on which the bond fingers are not formed before the step of providing the circuit board.
The closing means can be removed before the step of fusing the conductive balls to the ball lands of the circuit board to form the input/output terminals.
The closing means can be also removed after the step of fusing the conductive balls to the ball lands of the circuit board to form the input/output terminals.
The closing means may be an insulating film, e.g., an ultraviolet tape, or a conductive metal thin film, e.g., copper.
According to the method for fabricating a semiconductor package of the present invention as described above, the semiconductor chip is located inside the through hole having a predetermined width formed on the circuit board. Accordingly, the thickness of the semiconductor chip is offset by that of the circuit board to make the semiconductor package remarkably thin. Further, one face of the semiconductor chip is directly exposed out of the encapsulant, to increase heat radiation, improving thermal and electrical performance of the semiconductor chip.
In addition, since the heat spreading plate or metal thin film can be formed one face of the circuit board or one side of the circuit board including the one side of the semiconductor, one side of the semiconductor chip can be protected from external environment and its heat radiation performance can be improved. Further, the metal thin film or conductive ink film is formed to ground the semiconductor chip without being electrically separated, raising the electrical performance thereof.
Meanwhile, the mold runner gate is not formed on the face of the circuit board on which the circuit pattern is formed so as to allow the number of the ball lands of the circuit pattern to be as many as possible. The mold runner gate may be formed on the face of the closing means on which the circuit pattern is not formed. This enables free designing of the mold runner.
In the step of removing the closing means, a punch may be used to perforate through the slot formed between neighboring substrips to separate one side of the closing means from the circuit board strip.
The circuit board strip is formed in such a manner that the plural substrips having the plurality of through holes are interconnected. Thus, tens to hundreds of semiconductor packages can be simultaneously fabricated using a single circuit board strip. Further, the punch perforates through the slot to easily and safely remove the cover lay tape, preventing or minimizing damages in the circuit board strip. Moreover, the ground ring or ground plane is formed on the circuit board strip so as to prevent the accumulation of static electricity in the step of molding. This effectively solves various problems including damage to the semiconductor chip and circuit pattern of the circuit board strip due to momentary discharging of static electricity.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.